1. Field of the Invention
The present invention relates to a thin film transistor and method for manufacturing the same, and more particularly, to a thin film transistor and method for manufacturing the same in which ion penetration from source and drain regions is suppressed, and stress generated from gate sidewalls and an interlayer dielectric film is suppressed.
2. Discussion of the Related Art
The reliability of a complementary metal oxide semiconductor (CMOS) device having high performance and high density is important. If the size of the device is reduced, the thickness of a gate oxide film is correspondingly thinned. However, a power source supplied through a power supplier is not decreased in proportion to the thickness reduction. Accordingly, electrical stress is generated that reduces the reliability of the gate oxide film.
FIG. 1 is a cross sectional view of a conventional thin film transistor.
Referring to FIG. 1, a gate oxide film 110 is formed on a semiconductor substrate 100. The top surface of the gate oxide film 110 is nitridized to form a first nitride layer 120. On the first nitride layer 120, a polysilicon layer 130 is formed. A pocket 140 is formed in a portion of the semiconductor substrate 100 below the edge of the gate oxide film 110 by implanting impurity ions, e.g., boron ions, using a tilt implantation method. Subsequently, a lightly doped drain (LDD) is formed in the semiconductor substrate 100 by implanting impurity ions onto the semiconductor substrate 100 using the polysilicon layer 130 as a mask. A spacer which comprises an oxide layer 160 and a second nitride layer 170 is formed on the sidewalls of the gate oxide film 110, first nitride layer, and polysilicon layer 130. Then, using the spacer 160 and 170 and the polysilicon layer 130 as a mask, impurity ions are implanted at a high density onto the semiconductor substrate 100 to form source/drain regions 180.
The first nitride layer 120 is formed to prevent ion penetration from the polysilicon layer 130 to the gate oxide film 110.
Although ion penetration from the polysilicon layer 130 to the gate oxide film 110 may be prevented, a other problems still remain, for example, ion penetration from the pocket 140, including the source/drain regions, to the gate oxide film 110, and electrical stress occurring to the gate oxide film 110.